The present invention relates to a nonvolatile semiconductor memory device. More particularly, the present invention relates to a nonvolatile memory device and systems and a reading method thereof
Semiconductor memory devices may be roughly classified into volatile memory devices and nonvolatile memory devices.
In case of the volatile memory devices, their reading and writing speeds are fast, while they have such a disadvantage that stored contents therein disappear at power-off On the other hand, in case of the nonvolatile memory devices, stored contents therein are retained even at power-off. For this reason, the nonvolatile semiconductor memory devices may be used to retain contents to be reserved irregardless of whether a power is supplied. The nonvolatile semiconductor memory devices may include Mask Read-Only Memory (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), and the like.
In general, the MROM, PROM, and EPROM are not free to be erased and written by a system itself, so that it is not easy for general users to update stored contents. On the other hand, EEPROM is capable of being electrically erased or written. Application of the EEPROM is widened to an auxiliary memory or to system programming where continuous updates are needed (flash EEPROM). In particular, a flash EEPROM (hereinafter, referred to as a flash memory) exhibits a higher degree of integration than a conventional EEPROM and thus is advantageous in large auxiliary memory applications.
Flash memories may be divided into a NAND flash memory and a NOR flash memory according to interconnections of memory cells and bit lines. The NOR flash memory consumes a much amount of current, so that it is not unfavorable for a high degree of integration. On the other hand, the NOR flash memory is advantageous for a high speed. The NAND flash memory consumes an amount of cell current less than the NOR flash memory, so that it is advantageous for a high degree of integration.
Each of memory cells of a flash memory has a floating gate or a charge trap layer between a bulk region and its control gate. The flash memory stores data by adjusting a threshold voltage of a memory cell via accumulation or trapping of charge on or in its floating gate or charge trap layer. This operation is so-called referred to as a write or program operation.
Each of programmed memory cells has one of threshold voltage distributions each corresponding to N program states or programmed data values (N being an integer greater than or equal to 2). At a program operation, the coupling may arise between a selected memory cell and adjacent memory cells. The coupling causes widening of each of threshold voltage distributions each corresponding to program states and narrowing of an interval between adjacent program states. Such coupling is referred to as the electric field coupling or F-poly coupling.
As due to the coupling, a variation of threshold voltages of adjacent memory cells is large and an interval between adjacent program states is narrowed, it is difficult to read out data from memory cells reliably. As the number of bits stored per cell increases, such a phenomenon may increase more and more.